Design Cycle Time to Tape Out Reduced to Two Weeks

Singapore, and Vancouver, BC, 8 November 2019 – CompoundTek, a global foundry services leader in emerging silicon photonic solutions (SiPh), today announces the tapeout of a reduced footprint grating coupler for photonic I/O. The grating couplers were designed and optimised using photonic inverse design (PID) in conjunction with Lumerical’s industry leading FDTD nanophotonic simulator. Lumerical’s PID capability enables photonic designers to rapidly develop entirely new functionality with improved performance, reduced footprint, and more robust manufacturability.

“With this successful tapeout in partnership with Lumerical, customers will be able to access Lumerical’s PID solution with confidence when taping-out to CompoundTek in the future. The integration into our design flow, design partners and open SiPh manufacturing platform ecosystem will accelerate the adoption of SiPh solutions for various applications ranging from datacom transceivers, smart sensor, bio-medical, automotive LiDAR, quantum computing and artificial intelligence,” said KS Ang, Chief Operating Officer, CompoundTek.

The SiPh grating coupler is a key functional block for photonic I/O, enabling light to be coupled from fibre into and out of a photonic integrated circuit. Unlike end-fire edge couplers, grating couplers can be located anywhere on chip, enabling additional applications such as sense and test. With this flexibility comes the requirement for reduced footprint while maintaining high coupling efficiency. However, with over 100 design parameters, grating couplers are geometrically complex, rendering traditional optimisation techniques impractical. Lumerical’s PID technology enables designers to automatically and reliably generate optimal grating couplers with hundreds of free parameters. Testimony to its effectiveness, CompoundTek’s SiPh new grating couplers have been reduced in size by 20x and promise improved coupling efficiency.

“These new grating couplers will enable our customers to create improved commercial designs with higher yields and faster time to market,” said Lumerical CTO, James Pond. “PID’s powerful optimisation algorithms leverage adjoint sensitivity analysis to explore design spaces that are impractical by other means. Coupled with Lumerical’s industry leading FDTD solver, PID enables designers to efficiently explore and optimise designs with hundreds or more design parameters. In contrast, traditional design approaches are limited to a small number of established device designs, exploring much smaller parameter spaces, typically fewer than ten parameters.”

Full press release below: