CompoundTek’s services to be offered as part of the company’s future-focused development in 8”/12” agnostic Silicon Photonics Wafer Test Hub

Singapore, 24 Sep 2020 – CompoundTek Pte Ltd, a global foundry services provider in emerging Silicon Photonics (SiPh) solution confirms its future-focused development for 8”/12” agnostic Silicon Photonics Wafer Test Hub. Expansion efforts will be centred on addressing two key areas of market demand – wafer-level edge coupling capability and test time reduction for commercial product companies.

Today, the SIPh wafer test is performed by vertical optical coupling of the light into the device under test (DUT), contrary to actual end-application where light is coupled horizontally into the device through the coupler at the edge of the die. Creating a mismatch between the wafer test environment and final application often leads to potential gaps in SiPh test coverage, reinforcing the need for real-world based test scenarios to screen out failures.

Development of CompoundTek’s new wafer edge coupling technologies is a game-changing solution that sets out to increase coverage of existing SiPh wafer test by including the detection of fails due to edge couplers.

Scheduled to be offered to key customers from Q1 2021, the wafer-level edge coupling capability is being developed alongside expansion efforts of the company’s Test Executive Systems (TES). Representing a key challenge to broader market SiPh adoption, long test time per wafer – varying from 36 hours to as long as 96 hours, depending on the test type needed and coverage, is unlike the well established CMOS logic product supply chain.

Long test time is attributed to the complex opto-electrical (DC and RF) tests, and without a standardised SiPh wafer test solution capable of balancing test coverage with competitive test time, successful integration of optical components on a chip for SiPh devices is delayed, creating roadblocks to mass-market adoption of SiPh technologies.

Recent breakthroughs by CompoundTek’s optimisation of its proprietary TES executive can potentially reduce customers’ product test time by up to 40% – to as short as 1.5 hours (from 2.5 hours) or 70 hours (from 96 hours). Enabling large volumes of device-performance data necessary to carry a design from concept to qualification and subsequently into production, TES aims to accelerate market adoption of wafer-level SiPh test services.

Full press release below: