CompoundTek today successfully delivered prototypes targeting 200G/lane data transmission rate to two lead data-center customers. These products target next-generation 1.6T optical transceivers and extend the capabilities of silicon for pluggable transceivers and Co-Packaged Optics (CPO) in datacenters.

The products were manufactured using CompoundTek’s advanced silicon photonics process with 193nm ArF lithography and copper interconnects, proven 1n mass production. CompoundTek supports MPW and dedicated runs that enable customers to rapidly prototype designs and proceed to mass production with high yields.

Alcyon Photonics and CompoundTek have partnered to offer an extensive product portfolio that empowers the development of reliable photonic integrated circuits (PICs) with qualified designs. Alcyon leverages diverse design techniques to maximize the performance of building blocks while tailoring their features to match the unique requirements of each platform and process constraints. CompoundTek is a global foundry services leader in emerging silicon photonic solutions (SiPh)
delivering revolutionary semiconductor applications designed to meet critical requirements in high bandwidth and high data transfer solutions. The company’s know-how ranges from proprietary fabrication process expertise to design support for end-product manufacturing. The partnership between the two companies has led to the creation of a robust component library, offering key  functionalities with competitive performance and rapid fabrication timelines.

What’s inside it?

Alcyon’s IP Library for Compoundtek encompasses a collection of innovative designs protected either through patents or by a trade secret protocol. The library offers a set of functionalities under the SOI platform covering key passive operations present in current photonic integrated circuits: from basic structures (MMIs, DCs,..) to more complex functions such as mode (de)multiplexers, polarization converters and splitters. Alcyon’s IP Library for CompoundTek is in  continuous development to expand the functionalities offered and to further improve performance. The roadmap includes the expansion of C-band functionalities as well as
the development of high-bandwidth and polarization management devices for the Oband, which will be essential for future communication applications, sensing or Lidar.

“Our IP Library for CompoundTek evolves to deliver reliable, scalable designs, advancing C- and O-band solutions for future communications, sensing, and LiDAR.”

What are the main features of this library?

Alcyon’s IP Library for CompoundTek has been developed focusing on two main aspects that are cornerstone of a mature and competitive portfolio:
➢ Performance: Alcyon applies its extensive know-how in photonic design to offer cutting-edge components, using the most convenient techniques in each case while keeping in mind feasible sizes and fabrication process limitations.
➢ Reliability: unexpected performance of any device can make a complete PIC useless, which makes reliability an essential feature of any commercial library.

✓ Experimental validation: experimentally validating the designs and testing their replicability across different chips and fabrication batches is a key turning point. It  provides users with reliable information, accounts for real-world variability and ensures  consistent device performance across diverse applications.

By bridging the gap between simulation and real-world implementation, Alcyon equips its users with tools that are both innovative and reliable, ensuring consistent performance across diverse applications.

LIBRARY PERFORMANCE

In photonic integrated circuit design, each component plays a crucial role in determining the system’s overall functionality and efficiency. The Alcyon IP Library for CompoundTek makes use of sub-wavelength grating (SWG) technology to cover many key passive functionalities present in  photonic circuits and offers validated components that are ready to be included in any circuit-level application in a scalable way. The following sections describe these functionalities and show the experimental validation of the offered devices, including their characterization across different chips, demonstrating consistent performance with a scalable foundry process. The Alcyon IP Library includes power management and routing devices such as directional couplers, 1×2 and 2×2 multimode interferometers as well as polarization control building blocks such as polarization beam splitters and polarization converters. Further work is currently being carried out to not only improve the performance of the currently available devices but also expand the functionalities by adding new building blocks to the Alcyon IP Library for CompoundTek.

Power management and routing

Optical power management, particularly routing power along multiple paths, is a fundamental function in nearly all photonic integrated circuits. As a result, building blocks like power splitters and combiners are essential for achieving high-performance and scalable photonic systems. These  functions are typically realized using directional couplers (DCs) or multimode interference couplers (MMIs), which are widely used in applications such as transceivers, wavelength division multiplexing (WDM) filters, sensors, reconfigurable circuits, and quantum photonics. Each application imposes  specific performance requirements on the devices it relies on.

The DC offered in the Alcyon IP Library for CompoundTek fabricated with 193 nm ArF lithography tool on a 220 nm SOI silicon platform achieves power splitting with a broad bandwidth and low wavelength dependency. The SWG DC offers tunability of the splitting ratio via a change in the length of the device (Figure 1), always maintaining a low splitting ratio deviation. The coupling ratio of the scalable 193nm ArF lithography-fabricated SWG DC is shown in Figure 2 with a comparison to the device patterned using electron beam lithography at Applied Nanotools (ANT) [1].

 

 

 

 

 

 

 

 

 

SEUNG HWAN KIM1,3,4, BEOMSU PARK1, JI WOON PARK1, HYO‑SEUNG PARK1, JUYEONG MOON1, SUNG HYEON JANG1, RAMADAS NAMBATYATHU2, ROBIN CHAO2, S GUNASAGAR2, HAN-YOUL RYU3,5, AND KYONG HON KIM1*

1PhotoniSol Inc. 30 Songdomirae-ro, Songdo-Smartvalley B422, Incheon, 21990 Republic of Korea 2CompoundTek, Pte Ltd., 5 International Business Park, 609914, Singapore 3Department of Physics, Inha University, Incheon 22212, Republic of Korea4 shkim@photonisol.com, 5hanryu@inha.ac.kr* kyongh@photonisol.com

Abstract: This paper presents an experimental demonstration of monolithically integrated optical isolator chips with sputter-coated Ce:YIG films on silicon waveguides, using the nonreciprocal phase shift effect of a Mach-Zehnder-type interferometer. A fully CMOScompatible optical isolator chip has been developed, achieving 27.7 dB of optical isolation and 6.4 dB of insertion loss at an input wavelength of 1550 nm. The isolator chip has an area of 220 × 1310 m² and can be readily integrated with other silicon photonic devices to enable complete photonic integrated-circuit applications. This initial result indicates that monolithically integrated optical isolators, produced via mass-producible sputtering to deposit MO films directly on silicon waveguides, are feasible for large-scale manufacturing. Additionally, chip performance can be further enhanced by optimizing waveguide structures and magneto-optic film-coating conditions. The high-temperature annealing processes commonly used to crystallize MO films can be replaced by localized laser annealing.

1. Introduction
Optical isolator chips are essential components of photonic integrated circuits (PICs), ensuring stable operation of the laser source by preventing back-reflected light from interrupting the laser and enabling proper optical signal processing. Complementary metal-oxidesemiconductor (CMOS)-compatible optical isolator chips are particularly important when various laser diodes, optical amplifiers, modulators, and multiplexing devices are integrated together to protect optical signal transmitters, ensure the stable flow of the laser beam in the intended direction, and properly control the flow of optical signals in desired directions by blocking unwanted leakage.

Various technical approaches have been demonstrated for developing integrated optical isolators, beginning with initial ideas for waveguide-type optical isolators [1,2]. Physical principles utilizing optical nonlinearity [3,4], photonic crystals [5], temporal modulation [6,7], optomechanical and acoustics[8 ‒10], non-Hermitian parity-time symmetry [11], and magnetooptic effect [12‒32] were used to demonstrate waveguide-type optical isolator chips. However, integrated schemes using magneto-optic (MO) films on silicon waveguides are the most promising for practical applications due to their energy-efficient, passive photonic-device performance [15‒32]. Two main approaches to MO-film-based optical isolator chips involve the nonreciprocal polarization rotation (NPR) and nonreciprocal phase shift (NPS) effects [1,2]. Integrated optical isolator chips built on silicon optical waveguides that utilize the NPR effect face difficulties with phase-matching conditions between the transverse-electric (TE) and transverse-magnetic (TM) polarization modes in planar waveguide structures. This results in very strict fabrication error margins, making NPR-based optical isolator chip manufacturing challenging and limiting achievable performance [12‒15]. NPS-based optical isolator chips that use optical interferometer structures have been considered easier to produce, and device performance has been demonstrated by research groups worldwide. Silicon waveguide-based optical isolator chips of micro-ring resonator (MRR), Mach-Zehnder interferometer (MZI) and multimode interferometer (MMI) types have been demonstrated with a magneto-optic film cladding, either by bonding or pulsed-laser deposition (PLD) of Ce:YIG films [16‒33]. In recent studies, a monolithic integration method for Ce:YIG films directly on silicon or silicon nitride waveguides using pulsed laser deposition (PLD) has been reported [21], demonstrating the feasibility of implementing high-performance optical isolators without wafer bonding. The PLD method is considered unsuitable for mass-production film coating in conventional CMOS processes.

The sputtering method is widely used in conventional CMOS processes for thin-film deposition. Sputtered europium-substituted cerium iron garnet (Ce:EuIG) films have been used in MRR-type isolator chips [31], but neither Ce:YIG nor Ce:EuIG films have been used in MZItype isolator chips. MRR-type isolator chips have an extremely narrow isolation bandwidth and are highly sensitive to environmental conditions, thereby limiting their practical use. By  contrast, MZI-type isolator chips have a relatively wider isolation bandwidth and are less sensitive to environmental conditions.

In this paper, we present an experimental demonstration of MZI-type optical isolator chips based on the NPS with directly sputtered Ce:YIG films on silicon waveguides. These chips can be manufactured relatively easily using standard CMOS processes and sputter-deposited magneto-optic films on silicon waveguides. It will be demonstrated that our isolator chips achieved an optical insertion loss of 6.4 dB and an isolation of 27.7 dB, with a footprint of 220 × 1310 m². Details of the device structures and the experimental results will be provided in the following sections.

2. Device concept and operating principle

In this research, we have focused on demonstrating MZI-type optical isolator chips based on the NPS, with directly sputtered Ce:YIG films on silicon waveguides. These chips can be manufactured relatively easily using standard CMOS processes and sputter-deposited magnetooptic films on silicon waveguides. The device scheme and optical microscope image of the isolator chip are shown in Fig. 1. It consists of two 1 × 2 multi-mode interferometers (MMIs) for input and output coupling ports of an MZI, which includes an NPS section with the MO cladding on each arm and a reciprocal phase shift (RPS) section on one arm. Grating couplers (GCs) are formed for input and output beam couplings. The total chip dimensions are 220 m in width and 1310 m in length, excluding the GCs, where the MO section length is 1000 m.

2.1 Nonreciprocal phase shift (NPS)-based optical isolator

The optical isolator chip is designed to operate on the basis of the optical interferometer characteristics of the NPS effect in a silicon waveguide with an MO  cladding. A forward beam  passing through the chip undergoes constructive interference at the opposite output port due to  the accumulated phase shift through the NPS and RPS sections, while the reverse beam experiences destructive interference from the accumulated phase shift. A key feature of our devices is the use of monolithically coated MO cladding directly on the silicon waveguides,  fabricated by sputtering. Unlike MO film bonding or pulsed laser deposition (PLD), sputtering  can be easily adapted to conventional CMOS and mass-production processes. Key technical  challenges include the formation of high-quality, low-loss MO films on silicon waveguides to achieve the required optical isolator chip characteristics.

2.2 TM mode operation and NPS mechanism

The isolator chip was designed and analyzed to exploit the NPS characteristics of TM-polarized beams. For TM-mode beams, the electric-field component is  distributed upward along the  waveguide, enabling interaction with the MO film on the top cladding. This structural geometry induces the NPS effect on the propagating beam along the silicon-core waveguide via magnetooptical effects within the MO film. Figure 2(a) shows a cross-sectional schematic of the silicon  waveguide and MO film  cladding used in this study. An MO film was directly deposited onto the silicon waveguide by  sputtering, and the stacked structure was designed to allow the TM-mode field to overlap with the MO film. A cross-sectional scanning electron microscope (SEM) image of the fabricated waveguide structure is shown in Fig. 2(b), confirming that the MO film was uniformly deposited on the silicon waveguide. A SEM image of the deposited MO film surface shown in Fig. 2(c) indicates that the sputtering process provides a continuous and uniform morphology of the MO films deposited on silicon wafers. Figure 2(d) is a top-view SEM image of the MO

 

 

 

 

 

 

 

 

 

 

 

film deposited directly on the silicon waveguides, confirming that the film was properly formed along the waveguide pattern.
The isolator chip exploits the NPS effect of two oppositely propagating TM-mode beams when an external magnetic field is applied perpendicular to the beam propagation. The phase  shift accumulates along the waveguide propagation distance and is proportional to the Faraday  rotation characteristics of the MO film cladding, the mode confinement factor in the clad region, and the waveguide geometry. In the following section, we numerically analyze the NPS  characteristics by accounting for these factors and verifying the validity of the optical isolator design.

3. Waveguide design and numerical simulation

In this section, we numerically analyze the optical mode characteristics of a silicon waveguide clad with a sputter-coated MO film and calculate the magnitude of the NPS for a TM-mode beam propagating along the waveguide. We evaluate the TM-mode profile and beam confinement factor within the MO thin film as a function of the waveguide geometry. Based on these results, we design a suitable optical isolator chip structure.

3.1 Silicon waveguide geometry and mode analysis

We considered silicon waveguides fabricated on silicon-on-insulator (SOI) wafers with a cerium-substituted yttrium iron garnet (Ce????Y3−????Fe5O12, Ce:YIG) MO film deposited on the cladding. As reported in previous publications, a yttrium iron garnet (YIG) film was first deposited on top of the silicon waveguide as a buffer layer to alleviate the lattice mismatch between the silicon wafer and Ce:YIG film. The SOI wafer had a top-silicon thickness of 350 nm and a 2-m-thick buried oxide (BOX) layer. The waveguide width was set to 450 nm, which ensures stable TM-mode propagation in the 1.5-m optical communication wavelength range
while also providing sufficient electromagnetic field overlap within the upper MO film. Numerical analysis was performed by calculating the eigenmodes in the waveguide crosssection, and the mode profile was analyzed for the TM mode. In the numerical simulation, a Faraday rotation (FR) value of 200 deg/cm was applied to the YIG buffer layer, while that of −3000 deg/cm was applied to the upper Ce:YIG film. These settings ensured that the Ce:YIG layer predominantly induced the NPS effect.

3.2 TM-mode profile and confinement in YIG and Ce:YIG films.

The TM-mode beam profiles were calculated in the silicon core waveguide, the YIG buffer, and the Ce:YIG MO clad films to determine the mode confinement factor in the MO films, as  shown in Fig. 3. The silicon core waveguide had a thickness of 350 nm and a width of 450 nm.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The YIG buffer layer had a thickness of 30 nm, and the Ce:YIG MO film layer had a thickness of 200 nm. The calculated results show that the TM-mode confinement in the YIG layer is 8.5%, while the upper Ce:YIG layer exhibits 8.7% mode confinement. Similar levels of mode confinement were observed in both layers, indicating that the optical mode is effectively distributed throughout the magnetic thin-film stack. Since the FR value of the YIG film is much smaller than that of the Ce:YIG films, the upper Ce:YIG layer plays a dominant role in the formation of NPS. Therefore, the subsequent analysis of NPS characteristics focuses on the magneto-optical properties of the Ce:YIG layer.

3.3 Simulated NPS and phase accumulation

To quantitatively assess the NPS induced in the silicon waveguide with the Ce:YIG MO clad film, we calculated the NPS per unit length for the TM-mode beam. The NPS was derived from the difference in propagation constants along the propagation direction under an applied external magnetic field perpendicular to the beam propagation, and the phase accumulation characteristics along the waveguide length were also analyzed. The calculated results are shown in Fig. 4 as a function of waveguide width. The calculated NPS per unit length is approximately 65 deg/mm when the waveguide width is 450 nm. This indicates that the phase accumulation
required for 90-degree operation in the MZI-type optical isolator is achievable even at relatively short propagation lengths. As shown in these numerical analysis results, this study confirmed that a silicon waveguide structure integrated with sputtered YIG and Ce:YIG thin films can provide sufficient phase characteristics for implementing NPS-based optical isolators. In the following sections, we fabricate a device based on these design results and experimentally verify the optical isolator’s performance.

4. Device fabrication and material characterization

This section describes the process flow for an optical isolator fabricated on a silicon photonics platform and the characteristics of the MO film deposited by  sputtering. The silicon waveguide was fabricated using standard commercial foundry processes, and subsequent process steps optimized MO film deposition and thermal treatment conditions to achieve non-reciprocal optical transmission.

4.1 Device fabrication on a silicon photonics platform

The starting material was 200 mm diameter SOI wafers with a 350 nm thick top silicon layer on a 2 μm thick buried oxide layer. A 3-mask layer process was used to fabricate the waveguide layers, including grating couplers, rib and strip waveguides. This process was adapted from an  existing production silicon photonics process used at the foundry, with necessary recipe  adjustments to minimize development effort.

An initial 10 nm thick thermal oxidation stress relief layer was formed, followed by a 100- nm-thick low-pressure chemical vapor deposition (LPCVD) silicon nitride (Si3N4) layer. This  Si3N4 layer was used as a hardmask to etch 40-nm-deep trenches for grating couplers and partial etches of rib and strip waveguides. The lithography step to etch the Si3N4 hardmask and silicon was performed on a dry 193 nm ArF scanner capable of a minimum feature size of 65 nm. The  use of ArF lithography, rather than conventional Deep UV (DUV) lithography for the 1st mask  layer, improved silicon sidewall roughness, resulting in reduced optical  scattering. To ensure a  silicon loss of 40 nm thickness, the etch time was calibrated with a pilot wafer run. SEM crosssections were used to validate ellipsometry measurements. Following this, the photoresist was removed, and a 2nd mask layer was patterned for the rib waveguides using a 248 nm DUV  scanner lithography. A 130 nm deep silicon etch was then performed to form rib waveguides  with a net step height of 170 nm. After a photoresist strip, a 3rd DUV lithography step was used  to form strip waveguides with an etch depth of 280 nm. This final layer formed the waveguides  on which the MO film deposition would later be sputtered. At this stage, the Si3N4 hardmask was removed from the waveguides using a hot phosphoric acid etch. Throughout the process, pilot wafers were used to fine-tune the process recipes to meet required targets. Critical process  monitoring parameters such as post-lithography resist dimensions, post-etch silicon thickness  and post-etch feature sizes were closely monitored, along with SEM cross-sections to verify  waveguide and dielectric film thicknesses.

A final cladding layer of high density plasma (HDP) SiO2 was deposited on the waveguides  and the wafers were planarized to a thickness of 0.8 μm using chemical-mechanical polish  (CMP). Windows were then etched using a 4th mask layer in the regions required for MO film  deposition. The window opening was created through a combination of an initial dry plasma  etch followed by a wet etch using buffered oxide etch (BOE) to prevent sputtering damage to  the silicon waveguides during the dry etch process. After the foundry process was completed, the wafer was separated into individual chips, followed by the subsequent MO film deposition process.

4.2 Sputter deposition of YIG and Ce:YIG thin films

A 32-nm-thick YIG buffer layer was deposited on the silicon waveguides using RF sputtering  with a 2-inch-diameter Y3Fe5O12 (YIG) target at a working pressure of 3 mTorr and gas flows  of 96 sccm Ar and 4 sccm O2. The RF power was 80 W at room temperature, and the deposition  rate was approximately 0.9 nm/min. The YIG film was thermally annealed at 800 C in a tube  furnace for 120 minutes. Then, the Ce:YIG film was deposited on top of the YIG films using RF sputtering with a 2- inch diameter Ce1Y2Fe5O12 (Ce:YIG) target at the same working pressure of 3 mTorr and 100 sccm Ar gas flow. The RF power was 140 W at room temperature, and the deposition rate was approximately 3.7 nm/min. The 188-nm-thick Ce:YIG film was thermally annealed at 725 C  in a rapid thermal annealing furnace for 10 minutes. As shown in the SEM images in Figs. 2(b)- (d), the MO films were coated uniformly over the silicon waveguide. This sputtering- ased integration method simplifies the process by enabling direct application of the MO film to the  silicon waveguide structure without wafer bonding.

4.3 Rapid thermal processing and annealing optimization of Ce:YIG flms

To improve the magneto-optical properties of the sputtered Ce:YIG films, a rapid thermal processing (RTP) step was performed. The thermal treatment was performed in a two-step  process: a 725 °C anneal for 9 minutes under vacuum, followed by a 1-minute anneal at the  same temperature under a 1.5 mTorr oxygen atmosphere. Figure 5 shows the changes in  measured Faraday rotation characteristics as a function of the heat treatment period in the  oxygen environment for relatively thick MO films of 48-nm-thick YIG and 387-nm-thick Ce:YIG. Under the given thickness conditions, the vacuum 9-minute and oxygen 1-minute heat treatments produced the best magneto-optical properties, and at this time, a Faraday rotation  value of approximately 2940 deg/cm was measured at a wavelength of 1550 nm. Based on these  results, the same heat-treatment conditions are applied as those identified as optimal for  subsequent device fabrication. For the demonstrated integrated optical isolator device, relatively thin magnetic films of 32-nm-thick YIG and 188-nm-thick Ce:YIG were coated on the silicon waveguides to achieve a low-loss condition. In this case, the same RTP conditions were applied, but the Faraday rotation value decreased slightly to approximately 1905 deg/cm due to the reduced film thickness. This decrease may be attributed to differences in film thickness and suboptimal thermal conditions.

 

 

 

 

 

 

 

 

 

 

It is important to note that the thermal annealing temperature used in this study is relatively high compared to typical CMOS back-end process limits. To further enhance CMOS compatibility and reduce the thermal budget, alternative crystallization methods such as  localized laser annealing might be considered. Laser  annealing allows for selective heating of  the MO film while minimizing thermal effects on the surrounding silicon photonic structures  and has recently been shown as a promising technique for crystallizing Ce:YIG films deposited on non-garnet substrates [32]. The combination of localized laser annealing techniques with a
proper vacuum chamber and oxygen environment, as used in the rapid thermal processes in this research, could offer a feasible pathway to fully CMOS-compatible monolithic integration of magneto-optical isolators.

4.4 Characterization of magneto-optical properties of the Ce:YIG thin films

The magneto-optical properties of the Ce:YIG thin film were evaluated using Faraday rotation (FR) measurements. Figure 6 shows the experimental setup used for the FR measurements. A linearly polarized superluminescent laser diode beam at 1550 nm was sent through the MO film  sample placed between a pair of electromagnets under an applied external magnetic field, and  the polarization rotation of the transmitted light was measured with a Wollaston polarizer and  a balanced amplified photodetector.

The measured Faraday rotation curve for the 32-nm-thick YIG and 188-nm-thick Ce:YIG films coated on a silicon wafer is shown in Fig. 7. The saturated Faraday rotation value was  1905 deg/cm at 1550 nm, sufficient to provide the MO effect for the NPS-type optical isolator chip demonstration. Although the measured Faraday rotation value is lower than the maximum

 

 

 

 

 

 

 

 

 

of 2940 deg/cm for the 387-nm-thick Ce:YIG film, the 188-nm-thick Ce:YIG film was chosen to reduce optical loss in the given waveguide geometry because the optical waveguide loss with the MO clad increases as the Ce:YIG film thickness increases in the silicon core and stacked MO film structure. Therefore, in this study, considering the trade-off between Faraday rotation and optical loss, the 188-nm-thick Ce:YIG film was selected to demonstrate an optical isolator  chip with low insertion loss.

5. Optical Isolator chip performance.

The performance of optical isolator chips based on silicon waveguides with sputter-coated 32- nm-thick YIG and 188-nm-thick Ce:YIG clad films was characterized by measuring the transmittance spectra of the forward and backward beams through the chips under an external magnetic field of about 1500 Gauss. The measured transmittance spectra are shown in Fig. 8.

 

 

 

 

 

 

 

 

 

 

 

The maximum optical isolation was 27.7 dB, and the minimum insertion loss was 6.4 dB. The 20-dB isolation bandwidth was about 1.1 nm. This result indicates that monolithically  integrated silicon-waveguide isolator chips with a sputter-coated Ce:YIG film clad can be  successfully operated in photonic integrated circuit applications.

The insertion loss of the fabricated optical isolator chip was determined by measuring the  optical propagation losses of its individual waveguide sections. In Fig. 9(a), the measured propagation loss of the silicon waveguide with only SiO2 cladding is shown as a function of  waveguide length. The loss was found to be approximately −3.79 dB/cm, which results in about 1.0 dB of loss over the total waveguide length of 2600 μm for the isolator chip, as shown in Fig. 10. Figure 9(b) displays the propagation loss of the MO waveguide section where YIG and Ce:YIG thin films are coated on the silicon waveguide. The measured propagation loss in this MO-clad waveguide region was around −26.68 dB/cm, corresponding to roughly 2.7 dB loss over the 1000 μm-long MO interaction section used in the isolator structure.

Besides the propagation losses in the waveguide sections, the chip includes two multimode interferometers (MMIs) that act as the optical splitter and combiner at both ends of the Mach–

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ehnder interferometer setup. The excess loss from both MMIs was estimated at around 0.4 dB.

By combining these contributions, the isolator’s optical insertion loss, excluding the grating couplers, can be estimated. The silicon waveguide section with SiO2 cladding alone contributes approximately 1.0 dB, the waveguide section with MO cladding adds about 2.7 dB, and the MMI structures contribute roughly 0.4 dB of loss. Consequently, the estimated optical insertion loss of the isolator chip is around 4.1 dB.

However, the experimentally measured However, the experimentally measured insertion loss of the isolator chip was 6.4 dB, which exceeds the estimated internal loss. This discrepancy can mainly be attributed to two factors. First, the characteristics of the fabricated grating couplers were not uniform. Their insertion loss and coupling efficiency varied from chip to chip, potentially leading to inaccurate calibration of the grating coupler efficiency when determining the isolator chip’s insertion loss. Second, the fabricated chip did not meet the ideal nonreciprocal phase shift condition required for constructive interference in the forward direction of the Mach-Zehnder interferometer. If the phase shift deviates from the optimal value, some of the optical power may not be fully transferred to the output port, resulting in increased insertion loss.

Further improvements can be made by optimizing the thicknesses of the YIG and Ce:YIG films coated on the silicon waveguide and their thermal treatment conditions. An optimized silicon waveguide design, together with ideal MO film conditions, is essential for maximizing  the Faraday rotation properties of the Ce:YIG-film-coated silicon waveguide and for demonstrating compact optical isolator chips.

Table 1 summarizes a comparison between the optical isolator chip implemented in this study and representative SOI-based integrated optical isolators previously reported. Previous studies achieved isolation levels of 20-30 dB and operating bandwidths exceeding several nanometers but required relatively limited integration processes such as wafer bonding or PLD. Some studies have reported very low insertion losses in isolator devices fabricated from SOI wafers with a 220-nm-thick top silicon layer. However, these insertion loss values were measured relative to the insertion loss of a silicon reference waveguide with the same dimensions but with either a SiO2 or an air cladding. Isolator devices based on SOI wafers with top MO cladding are effective for TM-mode beams. Unfortunately, silicon waveguides made with SOI wafers having a 220-nm-thick top silicon layer themselves have relatively high propagation loss for TM-mode beams. This is why SOI wafers with a 350-nm-thick top silicon layer were used in our isolator fabrication to reduce propagation loss across the entire waveguide.

 

 

 

 

 

 

 

 

 

 

This study aimed to demonstrate the feasibility of monolithically integrated MZI-type optical isolator chips with sputter-coated MO film clad. We anticipate that silicon-waveguidebased optical isolator chips with sputter-coated MO films can be further improved for compact, fully integrated PICs. There remains ample room to improve the MO properties of the YIG and Ce:YIG films, as well as the silicon waveguide devices, to achieve such high-performance  isolator chips. In this study,    have not considered the wideband characteristics of the MZItype optical isolators. The 20-dB isolation bandwidth can also be improved by appropriately
designing the silicon waveguide device and optimizing the MO film conditions.

6. Conclusion

In this study, we experimentally demonstrated an NPS-based integrated optical isolator by directly sputtering MO films onto a silicon waveguide. The YIG buffer and Ce:YIG MO films were sequentially deposited on a silicon waveguide structure fabricated using a standard silicon photonics foundry process. The magneto-optical properties of the Ce:YIG films were optimized  via rapid thermal annealing processes.

Numerical analysis of mode confinement and NPS characteristics in TM mode confirmed that an NPS of approximately 65 deg/mm per unit length could be achieved at a waveguide  width of 450 nm. In the actual fabrication of the optical isolator device, considering optical loss  in the waveguide/MO stack structure, 32 nm YIG and 188 nm Ce:YIG magnetic films were used. The Ce:YIG film exhibited a Faraday rotation of 1905 deg/cm at 1550 nm.

The fabricated optical isolator achieved a maximum isolation of 27.7 dB and an insertion loss of 6.4 dB, with a 20-dB isolation bandwidth of approximately 1.1 nm. These results  demonstrate that monolithically integrated optical isolators can be realized on a silicon  photonics platform using a mass-producible sputtering process to deposit MO films on silicon  waveguide structures. The initial chip performance exhibited relatively high insertion loss and  a narrow isolation bandwidth; however, further improvements in high-performance isolator  chips can be achieved by optimizing the silicon waveguide structures, the MO film coating, and the thermal treatment conditions. These monolithic optical isolator chips will enable the broad  development of photonic integrated-circuit applications.

Funding. Korea Ministry of SMEs and Startups (MSS) (TIPS Program RS-2023-00302394, and RS-2024- 00447487), Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education (RS-2022-NR070869).

Acknowledgment. This work was supported partially by the Startup 1000 Project (micro DIPS #20279476) funded by the Ministry of SMEs and Startups through Seoul National University − System Semiconductor Industry Promotion Center. K.H. Kim thanks Mr. Jasper Leong at CompoundTek, Pte Ltd. for arranging collaborative foundry services.

Disclosures. The authors declare no conflicts of interest.

Data availability. Data underlying the results presented in this paper are not publicly available at this time but may  be obtained from the authors upon reasonable request Supplementary Document. See Supplement 1 for supporting content.

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15. K. Srinivasan, C. Zhgang, P. Dulal, et al., “High-Gyrotropy Seedlayer-Free Ce:TbIG for Monolithic LaserMatched SOI Optical Isolators,” ACS Photon. 6, 2455‒461 (2019).

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19. S. Liu, Y. Shoji, and T. Mizumoto, “TE-mode magneto-optical isolator based on an asymmetric microring resonator under a unidirectional magnetic field,” Opt. Express 30(6), 9934‒9943 (2022).

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To be held from 6-8 September at the at Shenzhen World Exhibition and Convention Center, the CompoundTek team will showcase its Silicon Photonics Foundry services and wafer testing solutions for prototyping and mass production at Hall 12, Booth 12D813.

As part of the exhibit’s highlight, CompoundTek is offering a free trial of its proprietary high-speed modulator IP/ an industry leading wafer-level edge coupling chip testing, to the first eight (8) customers who signs on for its upcoming MPW cycle.

Chat with us and find out how you can experience our one-stop Silicon Photonics services – a unique marketplace capability designed to bring your product to market in the shortest time.

Contact enquiries@compoundtek.com for more information. See you there!

Singapore, 23 May 2023 – CompoundTek Pte.Ltd (CompoundTek), a global foundry service provider in emerging silicon photonics (SiPh) solutions, formed a strategic collaboration with Ningbo Hyper–silicon Technology Co.Ltd, a China–based transceiver solution provider for data centres, to establish cost–effective high–volume SiPh Wafer Edge Coupling Test.

The partnership leverages CompoundTek’s existing wafer test solutions portfolio and aims to address the growing need for cost–effective testing capabilities with comprehensive coverage to identify known good dies at the wafer level and eliminate or reduce the need to perform die–level testing. It also taps into performance testing of the edge coupler, which is conducted in simulations akin to real–world or end–user applications, enabling SiPh product companies like Hyper–silicon to have faster yield feedback. Capturing potential excursions in the fab earlier minimises the cost of yield dropouts in the later stages of the packaging process.

Raj Kumar, Founder and Chief Executive Officer (CEO) of IGSS Ventures, the holding company for CompoundTek, and the company’s CEO said, “We have been working to push the present technical boundaries in SiPh testing that allow for SiPh mass productions and are excited to work with like–minded customers like Ningbo Hyper–silicon. CompoundTek believes technology innovations in cost–effective and efficient test strategies capable of detecting defective dies or dies that do not meet the expected performance at the wafer level are key to wider adoption in the SiPh wafer–level edge coupling test space.”

Ningbo Hyper–silicon’s Founder Yang Ming adds, “The high growth of demand for our product requires us to test our SiPh chips in both timely and cost–efficient ways to meet our end customer demand. A repeatable and reliable SiPh wafer–level electro–optical testing test platform is critical to achieving this goal. CompoundTek’s edge coupling wafer test solution meets our criteria, leading to improved quality control for the manufactured chips and identifying failures in the earlier assembly steps, allowing us to focus on Hyper–silicon’s core competencies in chip architecture and design.”

Today, integrating optical with electrical components on a single chip creates multiple new  challenges in wafer–level testing of SiPh devices as large volumes of optical, electrical and opto–electrical device–performance data are required at various stages of the product development life cycles, from prototyping to qualification and subsequently into production. Most companies have homegrown SiPh bench solutions, typically sufficient for small–scale engineering characterisation during the initial design verification phase but inefficient for the high–throughput and low–cost test required for testing from risk production to the mass production phase. Wafer–level edge coupling gives a higher test coverage than vertical coupling, traditionally used for coupling the light during wafer testing.

An agnostic SiPh wafer test service provider with a cost–efficient wafer test solution is needed to address market gaps, including for the largest SiPh product companies who had to make do with modified testers and limited in–house capabilities. Singapore–based CompoundTek has a portfolio of 20 global commercial customers and collaborates with over 20 research institutes and universities in various applications such as telecommunications, automotive radar, data communications, bio–sensing, artificial intelligence, quantum computing and smart sensors. The company is one of the few in the world with a dedicated SiPh water testing cleanroom offering state–of–the–art testing capabilities through multiple collaborations with specialised SiPh hardware testing
companies to leapfrog leading–edge capabilities.
For more information, please visit www.compoundtek.com and www.nc–opto.com .

Singapore, 08Nov2022–CompoundTek Pte Ltd, a global foundry services provider in emerging Silicon Photonics (SiPh) solutions will share its latest SiPh technology platform at the Ansys IDEAS Digital Forum to be virtually held on 6 Dec 2022.

The company looks to showcase its capabilities in the areas of Si photonics technology, enhanced PDK, latest 8”/12” on-wafer edge coupling testing capability at the event that will host global players in the electronic, photonic, and semiconductor design industries.

Singapore-based CompoundTek has over 25 global commercial customers across the telecommunications, automotive radar, data communications, bio-sensing, artificial intelligence (AI), quantum computing, and smart sensors industries. The company brings its commercialization capabilities to partnerships with over 25 research institutes and universities.

The IDEAS Digital Forum — a place to catch up on industry best practices and the latest advances in semiconductor, electronic and photonic design, will also explore future trends with keynotes from industry leaders. The event offers technical insights by expert chip designers from many of the world’s largest electronic and semiconductor companies and gives attendees a close-up view of some of the most advanced electronic design projects in the world.

Know about all this and more at the Ansys IDEAS Digital Forum 2022

Save the date/time: 6 December 2022.

https://www.ansys.com/events/ideas-digital-forum

18 new and enhanced components up the performance in both O and C wavelength bands

 Singapore, 03Nov2022–CompoundTek Pte Ltd, a global foundry services provider in emerging Silicon Photonics (SiPh) solutions announce that it has partnered with Seimens Digital Industries Software and Ansys-Lumerical to develop and release CompoundTek’s Process Design Kit (PDK) version3.0. With the vision of enabling best-in-class photonic circuit simulation for customers, PDK3.0’s Component Model Library (CML) offers new elements and enhanced performance.

Formerly Mentor Graphics, Siemens’ Electronic Design Automation (EDA) solutions provide a broad array of design and verification solutions for photonic designers, including L-Edit Photonics and LightSuite™ Photonic Compiler, both of which work with CompoundTek’s PDK 3.0. These tools provide productivity improvements for photonics experts and IC designers through automation and custom layout. Siemens’ Calibre® verification platform, which includes Calibre nmDRC with its proprietary equation based functionally, has extended its golden signoff status to include silicon photonic designs.

A total of 18 new components/enhanced performance in both O and C wavelength bands; SiNY-splitter, SOI Y-splitter, SiN MMI 1×1, SiN MMI 2×2, and new black box cells, etc., are added in this latest PDK release.

Singapore-based CompoundTek has over 25 global commercial customers across the telecommunications, automotive radar, data communications, bio-sensing, artificial intelligence (AI), quantum computing, and smart sensors industries. The company brings its commercialization capabilities to partnerships with over 25 research institutes and universities.

For more information on the Enhanced PDK version 3.0, please contact enquiries@compoundtek.com

• END –

About CompoundTek Pte Ltd

Founded and supported by industry veterans and technologists, Singapore-based CompoundTek combines world-class commercial foundry with leading silicon photonics (SiPh) research institutes to provide cutting-edge SiPh technologies that enhance foundry services capabilities. As one of the few companies offering SiPh solutions internationally, CompoundTek brings to the marketplace revolutionary semiconductor applications designed to meet critical requirements in high bandwidth and high data transfer solutions, particularly in emerging connectivity driving Industry 4.0. The company’s in-depth know-how includes end-to-end technologies – from proprietary fabrication process expertise to product design support with strategic partners and extended services for end-product manufacturing. CompoundTek’s global customers span leading brands and FORTUNE 500 companies in high-growth industries including artificial intelligence, automotive, bio-medical diagnostics, data center, lidar, smart sensors, telecommunication, and quantum optical computing.

Visit https://compoundtek.com/ for more information.

Note: A list of relevant Siemens trademarks can be found here.

Partnership innovates in enhanced test coverage and delivers cost efficiencies for reliable, high-volume testing

Singapore, 16June 2022 – CompoundTek Pte Ltd (CompoundTek), a global foundry service provider in emerging silicon photonics (SiPh) solutions, and STAr Technologies Inc (STAr), one of leading providers for semiconductor test solutions,today announced that they have successfully developed a groundbreaking Silicon Photonics (SiPh) Wafer Test Solution with automatic fibre array block edge coupling.

This breakthrough will help to address the need from SiPh product companies and manufacturers to be able to test the wafer as per howthe light is coupled into the SiPh product in the end application, thus expanding the test coverage capability of the wafer test.This ispossibly the only SiPh tester with the capabilityfor edge coupling fiber array automatically to SiPh ICs with trench width smaller than 100µm,which is of high repeatability and efficiency.

CompoundTek’s Chief Executive Officer, Raj Kumar, explained,“Testing the die using vertical grating coupler will compromise the test coverage of the wafer testing, as the test condition is not the same as per what it is going to be used in the field. Furthermore, designers will have to allocate space in the prime die for this vertical grating coupler and their test structure, increasing the die size as a result, while lowering gross die per wafer.”

“Skipping the wafer test totally will drive up the overall cost of products, as companies cannot identify SiPh known good dies before assembling with other dies, resulting in overall high costs and material wastage if a defective SiPh is assembled,” he added.

SiPh today is a technology that is not only used to displace traditional electrical interconnects, but also used in a broad range of applications, including lidar, quantum computing, and bio-sensing.However, the integration of optical components on a chip creates a host of new engineering and high-volume manufacturing challenges in wafer-level testing of SiPh devices as most of the products use an edge coupler to couple the light in and out of the chip. To go around the challenges of the edge coupler, most product companies either use vertical grating coupler during wafer test or choose to skip wafer test and only test after the SiPh test is assembled and packaged.

CompoundTek and STAr enable this technology with very precise positioningof fiber array block with accuracy and repeatability down to 0.1um, in a narrow trench of typically less than 100µm wide. The test fiberscan deflect the light at about 90 degrees into the edge coupler withlow optical power insertion loss and extremely low light reflection. This is enabled through patent-pending fiber alignment test kits and pattern recognition software that applies to all SiPh devices for both optical-optical and electro-optical tests.

STAr’sCEO and Founder, Dr Choon Leongsaid, “The jointly developed tester managed to address the technical challenges required for wafer-level efficient edge coupling testing with up to 50 per cent reduction in setup and alignment test time while keeping test system cost as low as 40 per cent lower than that of others available in the market. This partnership marks a new milestone for SiPh testing that successfully meets the market’spresent and future needs for a reliable and cost-efficient test system for both vertical and edge coupling, especially for high-volume testing. We believe that our test solutionhas hit the sweet spot in terms of meeting performance and cost requirements.”

The technology shift in the form of SiPh demonstrates the potential for measurable gains in speed, power efficiency and density. The first wave of the SiPh revolution is poised to roll over data centres around the world with optical interconnects that break the barriers set by copper wire. In parallel, the development of SiPh transceivers has resulted in increased demand forcost-effective wafer test solutions, enabling the industry to improve its quality control coverage at the wafer-level, potentially driving down product costs due to failures after packaging.

Singapore-based CompoundTek has a line-up of over 20 global commercial customers alongside collaborations with more than 20 research institutes and universities in various applications such as telecommunications, automotive radar, data communications, bio-sensing, artificial intelligence, quantum computing and smart sensors.

For more information, please contact enquiries@compoundtek.com

 About IGSS Ventures Pte Ltd

Singapore-based IGSS Ventures’ hybrid business and technology models enable the company to offer unique capabilities across two core segments namelyplant and fab/foundry transformation services and disruptive semiconductor technologies in applications that go beyond Moore’s Law. As a one-stop semiconductor solutions hub with three key subsidiaries, IGSSV’s differentiated business portfolio span:

1. IGSS which specialises inplant operational excellence and greenfield projects through our build-operate-manage-transfer (BOMT) approach;
2. IGaN which provides development and manufacturing on GaN-on-Si; and
3. CompoundTek offers co-design services, automated testing and commercialisation of silicon photonics (SiPh) with a dedicated 8” CMOS foundry.

 About CompoundTek Pte Ltd

Founded and supported by industry veterans and technologists, Singapore-based CompoundTek combines world-class commercial foundry with leading silicon photonics (SiPh) research institutes to provide cutting-edge SiPh technologies that enhance foundry services capabilities. As one of the elites offering SiPh solutions internationally, CompoundTek brings to the marketplace revolutionary semiconductor applications designed to meet critical requirements in high bandwidth and high data transfer solutions, particularly in emerging connectivity driving Industry 4.0. The company’s in-depth know-how includes end-to-end technologies – from proprietary fabrication process expertise to product design support with strategic partners and extended services for end-product manufacturing. CompoundTek’s global customers span leading brands and FORTUNE 500 companies in high-growth industries including artificial intelligence, automotive, bio-medical diagnostics, data centre, lidar, smart sensor, telecommunication and quantum optical computing.

Visit https://compoundtek.com/ for more information.

For media queries, please contactMs.Lalitha(lalitha@igssventures.com)

About STAr Technologies

Founded in 2000, and headquartered in HsinChu, Taiwan, STAr Technologies is a leader in semiconductor and test solutions;providing intellectual property, software, hardware, consumables, service and expertise to meet the requirements and challenges within the semiconductor industries. STAr’s global customers span leading foundries, IDMs, fabless companies in various market sectors across semiconductor industries including computing, memory ICs, telecommunications, industrial, automotive, CMOS imaging, data centres, smart sensors, etc.

Visit https://www.star-quest.com/ for more information.

For media queries, please contactstar_mkt@star-quest.com

Singapore, 13 April 2022– CompoundTek Pte Ltd (CompoundTek), a global foundry service provider in emerging silicon photonics (SiPh) solutions formed a strategic collaboration with Voyant Photonics (Voyant), a US-based revolutionary Light Detection and Ranging (LiDAR) solution provider to establish cost-effective high-volume SiPh Wafer Test for LiDar designed specifically for automotive as well as other fast-growing applications such as robotics and drones.

Addressing the growing need for consistency and reliability for LiDAR products, this collaboration aims to use SiPh wafer test as a cost-effective method to identify known good dies through stringent testing at elevated temperature to meet global quality requirement for automotive and industrial applications. Wafer-level testing also allows LiDAR product companies like Voyant to have faster yield feedback to capture potential excursion in the fab earlier and also minimise cost of yield dropouts in the later stages of packaging process.

LiDAR is a remote sensing method that uses a pulsed laser to measure distances and generate precise, three-dimensional map of geographical locations. This is commonly used today in autonomous vehicles, drones and robots to enable obstacle detection, avoidance, and safe navigation. SiPh is the choice of technology that LiDAR products use currently. It is leveraged on well-established silicon integrated circuits manufacturing process which are cost effective and relatively easy to manufacture.

IGSSV’s Founder and Group Chief Executive Officer, Raj Kumar, who is also CompoundTek’s Chief Executive Officer, said, “CompoundTek is thrilled to be working with Voyant to provide a cost-effective test strategy that is capable of meeting stringent international standards. The key to market wider adoption of wafer-level SiPh tests lies in the cost and efficiencies of the test. This is particularly true for LiDAR where comprehensive testing is done to meet the highest quality requirements for its end application, specifically in the automotive industry.”

Today, the integration of optical with electrical components on a single chip creates multiple new challenges in wafer-level testing of SiPh devices as large volumes of optical, electrical and opt-electrical device-performance data are required through various stages of the product development life cycles, from prototyping to qualification and subsequently into production. This is especially true for LiDAR, where it is used in automotive applications which demand higher level of stringent quality and reliability requirements than usual consumer products. Stringent wafer testing for defects is necessary as the consequences of test escapes can be very costly, not to mention hazardous and detrimental to life as well as property.

Most of the companies have homegrown SiPh bench solutions which are perhaps sufficient for small scale engineering characterisation during the initial design verification phase, but inefficient for the high-throughput and low-cost test required for testing from risk production to mass production phase.

Voyant’s Principal Engineer, Lawrence Tzuang, said, “The explosive growth of incorporating LiDAR in many applications requires us to test our SiPh chips in both timely and cost-efficient ways. A test platform that offers repeatable and reliable SiPh wafer level electro-optical testing is critical to achieve this goal. Working with a partner such as CompoundTek, which has both the test expertise and the capacity, allows us to focus on chip architecture and design, leading to both improved quality control for the manufactured chips and identifying failures in the earlier assembly steps.”

An agnostics SiPh wafer test service provider with a cost-efficient wafer test solution is needed to address market gaps including for the largest SiPh product companies who had to make do with modified testers and limited in house capabilities. CompoundTek and Voyant’s combined capabilities helps the industry to drive down associated product costs and time from product development cycle to mass manufacturing, and helps to accelerate the time to market.

Since its launch in 2017, Singapore-based CompoundTek has secured 20 global commercial customers and collaborates with over 20 research institutes and universities in various applications such as telecommunications, automotive radar, data communications, bio-sensing, artificial intelligence, quantum computing, and smart sensors. CompoundTek has invested in a dedicated SiPh water testing cleanroom with state-of-the-art testing capabilities through multiple collaborations with specialized SiPh hardware testing companies to spur leading-edge capabilities.

Press Release

PR_CompoundTek_Voyant Apr 2022 Final

For more information, please visit compoundtek.com and  voyantphotonics.com.

Know about all this and more at the Cadence Connect Event!

Save the date/time: 7 December 12.15pm – 12.45pm CET

CompoundTek’s Technology & Program Manager, David Ngo and Ansys’ Lead R&D Engineer Federico Duque Gomez will share industry insights and their thoughts on how a manufacturable Silicon photonics process design kit (PDK) offering is critical to a product company, right from prototyping to mass manufacturing in foundry. 

As a leading global Silicon photonics foundry provider, CompoundTek has been working closely with Electronics-Photonics Design Automation (EPDA) vendors including Cadence and Ansys-Lumerical to mature PDK to mainstream Si CMOS standard.

During this presentation, David and Federico will share an example of customized CWDM wavelength vertical grating couplers to meet O-band CWDM commercial customers requirement. 

The Photonic Inverse Design allows CompoundTek to enhance Silicon photonics PDK offerings and create manufacturable designs with minimum feature size enforcement in Ansys Lumerical shape and topology optimization, layout with Cadence EPDA software, silicon photonics validated in CompoundTek’s Si photonics foundry service  with fabrication, on-wafer 8”/12” agnostic testing hub measurement with commercialization of its new on-wafer wafer edge coupling technology.

Want to know more on the potential and future of Silicon Photonics PDK?